As the interconnect system in the back-end of integrated circuit (IC) chips shrinks, going from one technology node to the next, the line-to-line spacing between conductive lines also continues to shrink. As such, the dielectric thickness between the lines has presently reached values on the order ranging from about 90 nm to about 110 nm. Due to the desire to lower the line-to-line capacitance to minimize the RC time response of the interconnect network, low-k materials have been introduced as inter-metal-dielectrics. However, these new insulators no longer have the dielectric-strength of pure dense amorphous silicon oxides; their lower density and the presence of weaker bonds (such as Si—C bonds) introduce charge traps, and can potentially host mobile ions, that aid early breakdown events under electrical stress. In addition, the necessity for the integration of additional dielectrics films as etch-stop layers, and diffusion barriers on top of the copper metal lines, gives rise to interfaces that span between the lines and open new channels for early breakdown.
Since the profile of the etched trenches is often adjusted for copper filling optimization, in the damascene process presently used by most of the integrated circuit industry, the line-to-line spacing becomes even narrower at the top of the lines. This gives rise to the occurrence of the higher electric field near the interface between the low-k dielectric material and the diffusion-barrier/etch-stop layer above it.
Near the end of the fabrication of the microelectronic device, a dielectric test is conducted to determine both the quality and reliability of the dielectric. Usually, this test involves determining the electrical breakdown field of the dielectric within the test devices. The most commonly used model to predict the time to breakdown (tbd) for silica-based dielectrics under an electric field E, states that:                                           t            bd                    =                      A            ·                          ⅇ                                                                    Δ                    ⁢                                                                                  ⁢                                          H                      *                                                                                                  k                      b                                        ⁢                    T                                                  ⁢                                  γ                  ·                  E                                                                    ,                            (        1        )                            where A is a constant, ΔH* is the zero-field activation energy, γ is the field-acceleration parameter (which may be associated with the Si—O bond dipole moment that interacts with the electric field to lower the bond strength), kb is the Boltzmann constant, and T is the temperature in degrees Kelvin.        
For a given temperature T, γ(T) can typically be extracted from a series of time-dependent dielectric breakdown (TDDB) tests: A collection of devices under test (DUTs: capacitors, comb—comb or comb-serpent test structures), which are chosen to be uniformly distributed across the wafer, are stressed at a constant voltage and the time-to-breakdown distributions are recorded. By virtue of area scalability, these distributions should obey Weibull statistics. From the characteristic time-to-breakdown tbd(E), under various electric fields E, one can obtain the value of γ, and extrapolate the dielectric lifetime to operating voltage at any required confidence level.
Since TDDB tests are slow, one cannot test sufficient number of DUTs to obtain good enough statistics. Based on A. Berman paper (IEEE Proc. IRPS, 1981), one can ramp the voltage across a capacitor until breakdown. This test turns out to be a constant time measurement, where the voltage (or field) at which a breakdown occurs with that time window (which is dictated by the voltage ramp rate). The test does not allow the determination of γ, but is fast and allows testing a larger sample of DUTs.
However, given the reduced spacing between the conductive lines in today's microelectronic devices, the translation of an applied voltage to the actual electric-field experienced by the dielectric becomes very dependent on the exact minimum spacing between the conductive-lines. The spacing distribution would cause the measured breakdown voltages to be very wide, with many values appearing below the predefined allowed value, set by reliability and quality standards. Thus, in many instances, reliable devices are discarded as scrape although their dielectrics had no defects, thereby reducing device yield. This is highly undesirable given the cost of manufacture and the loss of potential profit.
Accordingly, what is needed in the art is an improved method determining dielectric reliability that does not suffer from the disadvantages associated with the processes discussed above.